module light(r2,r1,r0,l2,l1,l0,clk,i3,i2,i1);
input clk;
input i3,i2,i1;
output r2,r1,r0,l2,l1,l0;
reg r2,r1,r0,l2,l1,l0;
wire [1:0] a;
assign a[1]=(~i3&i2)|(i3);
assign a[0]=(~i3&~i2&i1)|(i3);
reg [2:0] q;
reg [2:0] state,next_state;
parameter
state0=3'b000,
state1=3'b001,
state2=3'b010,
state3=3'b011,
state4=3'b100,
state5=3'b101,
state6=3'b110,
state7=3'b111;
always @ (state)
begin
case (state)
state0:
begin next_state<=state1;end
state1:
begin next_state<=state2;end
state2:
begin next_state<=state4;end
state3:
begin next_state<=state6;end
state4:
begin next_state<=state1;end
state5:
begin next_state<=state2;end
state6:
begin next_state<=state4;end
state7:
begin next_state<=state6;end
endcase
endalways @ (state)
begin
case (state)
state0:q<=3'b000;
state1:q<=3'b001;
state2:q<=3'b010;
state3:q<=3'b011;
state4:q<=3'b100;
state5:q<=3'b101;
state6:q<=3'b110;
state7:q<=3'b111;
endcase
endalways @ (a)
begin
if (a==2'b00)
begin
r2=0;r1=0;r0=0;
l2=0;l1=0;l0=0;
endelse if (a==2'b01)
begin
r2=q[2];r1=q[1];r0=q[0];
l2=0;l1=0;l0=0;
endelse if (a==2'b10)
begin
r2=0;r1=0;r0=0;
l2=q[2];l1=q[1];l0=q[0];
endelse if(a==2'b11)
begin
r2=~clk;r1=~clk;r0=~clk;
l2=~clk;l1=~clk;l0=~clk;
end
endendmodule