Verilog實現Bresenham任意斜率直線

根據bresenham演算法原理：

簡單修改後支援任意斜率直線：

reg [15:0] dx;

reg [15:0] dy;
reg signed [15:0] ix;
reg signed [15:0] iy;
reg signed [15:0] iw;
always @(posedge clk)
begin
if (m_req == 1'b1) begin
dx <= ($unsigned(addr_x1) > $unsigned(addr_x0))?($unsigned(addr_x1) - $unsigned(addr_x0)):($unsigned(addr_x0) - $unsigned(addr_x1));//求絕對值
dy <= ($unsigned(addr_y1) > $unsigned(addr_y0))?($unsigned(addr_y1) - $unsigned(addr_y0)):($unsigned(addr_y0) - $unsigned(addr_y1));//求絕對值
ix <= ($unsigned(addr_x1) > $unsigned(addr_x0))?1:-1;//x軸步進
iy <= ($unsigned(addr_y1) > $unsigned(addr_y0))?1:-1;//y軸步進
iw <= ($unsigned(addr_y1) > $unsigned(addr_y0))?1280:-1280; //影象為1280*720
endendreg signed [15:0] n2dy;
reg signed [15:0] n2dydx;
reg signed [15:0] n2dx;
reg signed [15:0] n2dxdy;
reg signed [15:0] stepx;
reg signed [15:0] stepy;
always @(posedge clk)
begin
if (m_req_d1 == 1'b1) begin
n2dy <= (dy << 1);
n2dydx <= (dy - dx) << 1;
n2dx <= (dx << 1);
n2dxdy <= (dx - dy) << 1;
endendalways @(posedge clk)
begin
if (m_req_d1 == 1'b1) begin
stepy <= (dy << 1) - dx;
end else if (addr_wr) begin
if(cx != addr_x1 || cy != addr_y1)begin
if(dx>dy)begin
if(stepy > 0)
stepy <= stepy + n2dydx;
else
stepy <= stepy + n2dy;
end//dy>dx, stepy 常》0;
endend
endalways @(posedge clk)
begin
if (m_req_d1 == 1'b1) begin
stepx <= (dx << 1) - dy;
end else if (addr_wr) begin
if(cx != addr_x1 || cy != addr_y1)begin
if(dy>dx)begin
if(stepx > 0)
stepx <= stepx + n2dxdy;
else
stepx <= stepx + n2dx;
end//dx>dy, stepx 常》0;
endend
endreg [15:0] cx;
reg [15:0] cy;
always @(posedge clk)
begin
if (rst_n == 0 || m_req == 1'b1) begin
addr <= $unsigned(addr0[15:0])*1280 + $unsigned(addr0[31:16]);
cx <= addr0[31:16];
cy <= addr0[15:0];
end else if (addr_wr) begin
if(cx != addr_x1 || cy != addr_y1)begin
if(stepx > 0)//x軸誤差累計
cx <= cx + ix;
if(stepy > 0)//y軸誤差累計
cy <= cy + iy;
addr <= addr + ((stepx>0)?ix:0) + ((stepy>0)?iw:0);
endend
end

斜率

斜率<1: p0(100,200)~p1(300,300)

斜率》1: p0(200,100)~p1(300,300)

垂直: p0(300,100)~p1(300,300)

水平: p0(100,300)~p1(300,300)

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