非同步FIFO程式

module fifo(wr_clk,//write fifo clock

nwr, //write fifo signal
din, //write fifo data
rd_clk,//read fifo clock
nrd, //read fifo signal
dout, //read fifo data
full, // 1 = fifo full
empty);// 1 = fifo empty
input wr_clk, nwr, rd_clk, nrd;
input [bsize-1:0] din;
output [bsize-1:0] dout;
output full, empty;
reg full, empty;
reg [bsize-1:0] buff [dsize-1:0];
reg [asize:0] wr_addr_bin, rd_addr_bin;
reg [asize:0] sync_wr_addr0_gray, sync_wr_addr1_gray, sync_wr_addr2_gray;
reg [asize:0] sync_rd_addr0_gray, sync_rd_addr1_gray, sync_rd_addr2_gray;
wire [asize-1:0] fifo_entry_addr, fifo_exit_addr;
wire [asize:0] wr_nextaddr_bin, rd_nextaddr_bin;
wire [asize:0] wr_nextaddr_gray, rd_nextaddr_gray;
wire asyn_full, asyn_empty;
parameter
dsize = 256, asize = 8,
bsize = 8;
initial
begin
full = 0;
empty = 1;
wr_addr_bin = 0;
rd_addr_bin = 0;
sync_wr_addr0_gray = 0;
sync_wr_addr1_gray = 0;
sync_wr_addr2_gray = 0;
sync_rd_addr0_gray = 0;
sync_rd_addr1_gray = 0;
sync_rd_addr2_gray = 0;
endfifo資料的寫入與輸出//
assign fifo_exit_addr = rd_addr_bin[asize-1:0];
assign fifo_entry_addr = wr_addr_bin[asize-1:0];
assign dout = buff[fifo_exit_addr];
always @ (posedge wr_clk)
begin
if (~nwr & ~full) buff[fifo_entry_addr] <= din;
else buff[fifo_entry_addr] <= buff[fifo_entry_addr];
end///fifo讀寫的位址生成器///
assign wr_nextaddr_bin = (~nwr&~full) ?wr_addr_bin[asize:0]+1:wr_addr_bin[asize:0];
assign rd_nextaddr_bin = (~nrd&~empty)?rd_addr_bin[asize:0]+1:rd_addr_bin[asize:0];
assign wr_nextaddr_gray = (wr_nextaddr_bin >> 1) ^ wr_nextaddr_bin;
assign rd_nextaddr_gray = (rd_nextaddr_bin >> 1) ^ rd_nextaddr_bin;
always @ (posedge wr_clk)
begin
wr_addr_bin <= wr_nextaddr_bin;
sync_wr_addr0_gray <= wr_nextaddr_gray;
endalways @ (posedge rd_clk)
begin
rd_addr_bin <= rd_nextaddr_bin;
sync_rd_addr0_gray <= rd_nextaddr_gray;
end///採用雙鎖存器把非同步訊號同步起來/
always @ (posedge wr_clk)
begin
sync_rd_addr2_gray <= sync_rd_addr1_gray;//讀訊號同步到寫時鐘
sync_rd_addr1_gray <= sync_rd_addr0_gray;
endalways @ (posedge rd_clk)
begin
sync_wr_addr2_gray <= sync_wr_addr1_gray;//寫訊號同步到讀時鐘
sync_wr_addr1_gray <= sync_wr_addr0_gray;
end/將產生的full訊號和empty訊號同步的各自的時鐘域上//
assign asyn_empty = (rd_nextaddr_gray==sync_wr_addr2_gray);
assign asyn_full = (wr_nextaddr_gray==);
always @ (posedge wr_clk)
begin
full <= asyn_full;
endalways @ (posedge rd_clk)
begin
empty <= asyn_empty;
end//endmodule

非同步FIFO程式

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